Timing Diagram Markup Language (TDML), Version 1.1-1-051899
Attribute: inverted (Inverted) | |||||||||
Definition: |
This attribute is a Boolean flag that controls the initial state of a clock type Signal <signal> and the order in which it begins oscillating between states. | ||||||||
Use: |
By default, a clock type Signal <signal> initially starts in a low state, then transitions to a high state after a delay time specified by Time Offset <time.offset> element. If this attribute is set to "1", the clock will initially start in a high state, then transition to a low state after its Time Offset <time.offset>. If this attribute is omitted a value of "0" is assumed. | ||||||||
Attribute Content: |
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Associated Elements: |
This attribute is associated with:
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Remarks: |
Standard Version: 1.0
Original version: February 1, 1999
Last updated: May 3, 1999 add attr. content
Timing Diagram Markup Language (TDML), Version 1.1-1-051899
Copyright © 1998, 1999 by Silicon Integration Initiative,
Inc. All rights reserved worldwide.