Timing Diagram Markup Language (TDML), Version 1.1-1-051899
Element: | Duty Cycle |
Tag: | <duty.cycle> |
Definition: |
This optional element defines the time during which a clock remains in a high state as a percentage of the period of the clock. If the clock is inverted, Duty Cycle describes the low time as a percentage of the clock period. |
Remarks: |
Duty Cycle is evaluated to a floating-point percentage value between 0 and 100. Example: an uninverted clock having a duty cycle value of "40", implies that the clock signal exhibits a logical high state for 40% of the clock period. If this element is not specified, or if it evaluates to null, the value for Duty Cycle is assumed to be 50%. |
Associated Attributes: |
None |
Element Content: |
|
SGML Model: | |
<!ELEMENT duty.cycle (%tdml.value.model;) > |
Standard Version: 1.0
Original version: February 1, 1999
Timing Diagram Markup Language (TDML), Version 1.1-1-051899
Copyright © 1998, 1999 by Silicon Integration Initiative,
Inc. All rights reserved worldwide.