Timing Diagram Markup Language (TDML), Version 1.1-1-051899
Attribute: vs (Vector State) | |||||||||||||||
Definition: |
This attribute represents the state of vector signals (bus signals) that cannot be represented using single-bit state values. | ||||||||||||||
Use: |
This attribute is typically specified as a binary or a hexadecimal number that specifies the state of several Signals <signal>s that are logically grouped together and represented as a single bus Signal <signal>. | ||||||||||||||
Attribute Content: |
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Associated Elements: |
This attribute is associated with:
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Remarks: |
Vector State attributes can be used to represent the states of individual Signals <signal>s with multi-valued logic systems that cannot be expressed using the "s" attribute. Examples of valid binary values are 'b0101 (unsized binary value) and 4'b0101 (sized binary value). Examples of valid hexadecimal numbers are 'hA (unsized hex value) and 4'hA (sized hex value). On sized values, the first digit indicates the number of bits in the Signal <signal>. An example of a non-standard logic system is a VHDL enumerated type value with legal values of START, STOP, and IDLE. |
Standard Version: 1.0
Original version: February 1, 1999
Last updated: May 3, 1999 add attr. content
Timing Diagram Markup Language (TDML), Version 1.1-1-051899
Copyright © 1998, 1999 by Silicon Integration Initiative,
Inc. All rights reserved worldwide.